Conventionally, when signals are delivered between circuit blocks having independent clock sources, i.e., clock domain crossing (CDC), verification requires consideration of clock domain differences. In other words, whether a reception-side circuit block operates properly with a signal delivered between circuit blocks different in clock cycle has to be verified.
With advancing circuit integration in recent years, logic design to produce one circuit under test that includes thousands of CDCs is no longer anything out of the ordinary. At locations where asynchrony is caused by CDC, a meta-stable state inevitably occurs due to a violation of setup time, hold time, etc. in a reception-side circuit block, bringing about a need of verifying in advance that malfunction does not occur even if a meta-stable state occurs.
A technique related to “CDC simulation” for simulating the randomness of signals received from a different clock domain in logic simulation has been disclosed as a means for carrying out verification on a mechanism of delivering signals between CDC circuit blocks. For example, a verification support apparatus has been disclosed that when detecting an output signal output from each transmission-side circuit element at a CDC, generates jitter of an arbitrary value for a given time and inputs the jitter to a reception-side circuit element (see, e.g., Japanese Laid-Open Patent Publication Nos. 2009-187119, 2009-187344, and 2009-93635). The jitter input virtually reproduces the meta-stable state resulting from signal delivery between CDC circuit blocks, enabling verification of whether the reception-side circuit element at the CDC operates properly when a meta-stable state is generated.
The conventional techniques, however, poses a problem in that an omission in verification is apt to occur if a transmission-side operation clock at a CDC is shorter in frequency than a reception-side operation clock. For example, during one cycle of the reception-side operation clock, the transmission-side operation clock may run plural cycles and output plural output signals. In such a case, only the jitter based on an output signal output from a transmission-side circuit element immediately before the rising edge of the reception-side operation clock is input to each reception-side circuit element.
Consequently, changes in signals other than the output signal output from the transmission-side immediately before the rising edge of the reception-side operation clock are not reflected on the reception-side circuit element, resulting in an omission in verification of instances of generation of a meta-stable state, thus a problem of lower verification efficiency arises.
As described above, to verify what effect each of the signals output at differing timings from the transmission-side circuit elements has on the operation of the reception-side circuit elements, CDC simulation must be repeated until the effect of each output signal output at each timing is reflected on the operation. Hence, simulation has to be repeated many times, which leads to an increase in the work load and the work time to carry out logic verification, inviting a problem of a longer design period.